The Real Time Interrupt
This interrupt exists to establish a heartbeat you can use to watch
time pass. The RTI interrupt is controlled by the TMSK2, TFLG2, and
PACTL registers, and the CCR I bit. Its interrupt vector is at fff0.
Setting the RTI Timer's Rate
This is set by the low order two bits of the PACTL register. We
probably want to set these bits both to 1, so we get an RTI interrupt
interrupt every 32.77 ms.
Enabling RTI Interrupts
Two things have to be done: the I bit in the CCR needs to be cleared
with a CLI instruction, and you need to set the RTII bit in TMSK2 to 1
(that's right it is backwards from the CCR I bit).
Responding to RTI Interrupts
You need to clear the RTIF flag to get another RTI interrupt. This is
done by writing a 1 to this bit (I know, it doesn't make sense). My
favorite way to do this is with a BCLR instruction trying to clear
every bit except the one you actually need to clear. This is because
of the implementation of the bclr instruction.