Something we haven't talked about much has been doing multiplication and division on the HC11. It turns out that this takes a bit of finagling to work right, and the multiplication and division instructions are a bit odd.
MULA basic problem with multiplication is that, in general, the result of a multiplication can be twice as wide as its operands. We already faced the problem of a result that's wider than the operands when we discussed addition and subtraction; in that case, we only produced one more bit than the width of the operands, so we were able to to tuck the bit away in the CCR.
In the case of multiplication, though, an eight bit operand times an eight bit operand can give us a 16 bit result (255 * 255 = 65025). So, we can't use a band-aid like the CCR; we really need to be able to handle a result that's twice as wide as the operands.
The MUL instruction does just that. The operands are in
the A and B accumulators (there are no other addressing modes
available), and the result is in the D accumulator.
The operands are interpreted as unsigned; the C bit is the only
condition code affected by the instruction, and it's used in a
completely unique way: it is set if the sign bit of the B accumulator
is set. The idea here is that we can get an eight-bit rounded result
with the adca instruction. The purpose is related to
floating point arithmetic, which we may get a chance to talk about
later...
You can also see that this is one of the most expensive instructions in the machine: it takes ten cycles. Multiplication really is harder than addition!
IDIV and FDIVThere are actually two division instructions, one intended for integer arithmetic and one intended for floating point.
IDIV
The IDIV instruction performs a 16 bit integer division.
Division has the opposite catch from multiplication: in division, you can't in general make any predictions in advance regarding the sizes of the operands and the results. Your denominator might really a 16 bit number, in which case the quotient will only be a couple of bits but your remainder can be 16 bits. On the other hand, if you're dividing by something like 3 then your remainder will be quite small, while your quotient can be close to sixteen bits.
Consequently, the HC11 uses the D and X registers as both operands and results. The numberator is initially in the D accumulator, with the denominator in the X. The quotient ends up in X, and the remainder in D.
The Z and C condition codes are modified by this instruction: Z is set on a remainder of 0; V is always cleared; C is set on a divide-by-zero.
This instruction is down-right painful to execute: 41 cycles.
FDIV
The FDIV instruction performs a sixteen bit floating
point division. We'll talk about this more if we get a chance...