RISC-V: An Open CPU Architecture

RISC-V is an open CPU architecture that is a neat development in the history of CPUs and computing. This page is a start of collecting information and links about it.

The RISC-V Home is always a good place to start.

Tutorials and Other Resources

This Medium post is a RISC-V assembly tutorial.

A RISC-V Assembly Manual is available; it looks to be unofficial but very comprehensive.

Another short RISC-V Assembly Tutorial is available at UTK. It refers to using a full RISC-V toolchain.

Simulators, Assemblers, Etc.

I have been trying to find a good RISC-V assembly simulator, but not having much luck. There are many functional instruction simulators, but they take a compiled binary as input, not the textual assembly language, which means you need some entire RISC-V toolchain to compile or assemble code into a correct binary executable file. I just want a simple assembly simulator!

The main RISC-V site can list simulators (and other tools).

The project Masimulator maybe does provide near-assembly simulation, but it uses (and embeds?) an assembler to produce a binary, but this simple toolchain may not be a bad way to go.

PyRISC is a python-based RISC-V simulator, but I am pretty sure it only uses binary executables as input, and so requires a compiler/assembler toolchain.

TinyFive simulators RISC-V instructions in Python, but seems oriented to AI-type applications, focusing on numerical operations in neural nets.

MARSS-RISC-V may be an option. MARSS has long been a decent MIPS simulator, so this port to RISC-V should be good.

This RISC-V ISA Model seems to be someone’s beginning attempt at some Python tool. It contains the defined components of the ISA, but that seems to be it. It might be something to build on.