The Real Time Interrupt
This interrupt exists to establish a heartbeat you can use to watch
time pass. The RTI interrupt is controlled by the TMSK2, TFLG2, and
PACTL registers, and the CCR I bit. Its interrupt vector is at
fff0 - fff1
.
Setting the RTI Timer's Rate
This is set by the low order two bits, RTR1 and RTR2, of the PACTL
register which is located at address 1026
. We
probably want to set these bits both to 1, so we get an RTI interrupt
interrupt every 32.77 ms; a little more than 3 percent of a sec.
Enabling RTI Interrupts
Two things have to be done: the I bit in the CCR needs to be cleared
with a CLI instruction, and you need to set the RTII bit in TMSK2 and
TFLG2 to 1 (that's right it is backwards from the CCR I bit).
Responding to RTI Interrupts
You need to clear the RTIF flag to get another RTI interrupt. This is
done by writing a 1 to this bit (I know, it doesn't make sense).
References
See M68HC11 Reference manual, pages 382 - 388.
Example
Here's an example, that uses the RTI interrupt:
rti.asm