Understanding and Improving Hardware Performance on Graph Algorithms

Revision as of 19:26, 17 November 2014 by Please (Talk | contribs)

(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search

Large parallel graph computations are becoming a major class of HPC computing efforts, yet it is known that such algorithms do not utilize standard hardware architectures very effectively. We are studying the low-level behavior of parallel graph algorithms in order to understand the hardware bottlenecks and improve both the hardware and the algorithms.