Yuho Jin

Assistant Professor

Department of Computer Science
New Mexico State University
P.O. Box 30001, MSC CS
Las Cruces, NM 88003-8001

Office: Science Hall (SH) 142
Email: yjin at cs.nmsu.edu
Voice: 575-646-1218
Fax: 575-646-1002
Office hours: Mon 4-5PM, Tue 2:30-3:30PM

CV (updated 8/26/2011)
Short Bio

Research Opportunities: I am actively recruiting motivated students who are interested in solving problems for designing heterogeneous multicore processors, architecting energy-efficient and cost-effective on/off-chip interconnection networks, and exploiting compiler/OS issues toward energy-efficiency. If you are interested, please email your CV to me.

Research Areas

Computer Architecture, Interconnection Network, Multicore Architecture, Parallel Computing

Publications

Communication-Aware Globally-Coordinated On-Chip Networks,
Y. Jin, E. J. Kim, T. M. Pinkston
IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol. 23, No. 2, February 2012
Thread Criticality Support in On-Chip Networks,
Y. Jin, R. Wang, W. Choi, T. M. Pinkston
Internatnional Workshop on Network on Chip Architectures (NoCArc), held in conjunction with MICRO-43, December 2010
Adaptive Data Compression for Low-Power On-Chip Networks,
Y. Jin, K. H. Yum, E. J. Kim,
Book chapter entitled Low Power On-Chip Network Designs, Springer, 2010
Integration of Admission, Congestion, and Peak Power Control in QoS-Aware Clusters,
K. H. Yum, Y. Jin, E. J. Kim, and C. R. Das,
Journal of Parallel and Distributed Computing (JPDC), Vol. 70, No. 11, July 2010
A Framework for End-to-end Simulation of High-Performance Computing Systems,
W. E. Denzel, J. Li, P. Walker, Y. Jin,
Simulation: Transactions of the Society for Modeling and Simulation International, 2010
Design and Analysis of On-Chip Networks for Large-Scale Cache Systems,
Y. Jin, E. J. Kim, K. H. Yum,
IEEE Transactions on Computers (TC), Vol. 59, No.3, March 2010
Recursive Patitioning Multicast: A Bandwidth-Efficient Routing for Networks-On-Chip,
L. Wang, Y. Jin, H. Kim and E. J. Kim,
International Symposium on Networks-On-Chip (NOCS), May 2009
Adaptive Data Compression for High-Performance Low-Power On-Chip Networks,
Y. Jin, K. H. Yum, E. J. Kim,
International Symposium on Microarchitecture (MICRO), November 2008
A Framework for End-to-end Simulation of High-Performance Computing Systems,
W. E. Denzel, J. Li, P. Walker, Y. Jin,
International Conference on Simulation Tools and Techniques for Communications, Networks, and Systems (SIMUTools), March 2008
A Domain-Specific On-Chip Network Design for Large-Scale Cache Systems,
Y. Jin, E. J. Kim, K. H. Yum,
International Symposium on High-Performance Computer Architecture (HPCA), February 2007
I/O Node Placement for Performance and Reliability in Torus Networks,
T. Azeeze, H. Kim, Y. Jin, E. J. Kim,
International Conference on Parallel and Distributed Computing and Systems (PDCS), November 2006
Peak Power Control for a QoS Capable On-Chip Network,
Y. Jin, E. J. Kim, K. H. Yum,
International Conference on Parallel Processing (ICPP), June 2005
IBM Austin Conference on Energy-Efficient Design (ACEED), March 2005

Yuho Jin

Research Areas

Publications

Teaching