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References:

[1] Geva, Robert (Intel); Morris, Dale (Hewlett-Packard) IA-64 Architecture Disclosures White Paper

[2] Intel   IA-64 Application Developer's Architecture Guide, Rev. 1.0

[3] Intel and Hewlett-Packard   IA-64 Application ISA Guide 1.0

[4] Sharangpani, Harsh  Intel Itanium Processor Microarchitecture Overview  Intel Corporation

[5] Doshi, Gautam  Understanding the IA-64 Architecture   Intel Corporation  August 31, 1999

[6] Dulong, Carole  IA-64 Architecture Innovations  Intel Corporation  February 19, 1998

[7] Pylkin, Alexei   Merced Facts and Speculations   Supercomputer Software Department RAS 

http://www.microprocessor.sscc.ru/Merced/

[8] Wolfe, Alexander   Intel's 64-Bit Merced: Software Matters (Compilers Slighted in Rush to Cover Parallelism     Byte.Com, April 12, 1999

http://www.byte.com/columns/wolfe/1999/04/0412wolfe.html

[9] Wolfe, Alexander Internal Layout of Intel's Merced Comes to Light    EEtimes,  September 28, 1998

http://www.eetimes.com/news/98/1029news/internal.html

[10] Every, David K.  IA64 (EPIC) is RISC  MacKiDo, November 10, 1998

http://www.mackido.com/Hardware/EPICisRISC.html

[11] Crawford, John and Huck, Jerry      Next Generation Instruction Set Architecture

Links:

The following is a local copy of an extensive tutorial of the IA-64 architecture created by Intel. The original tutorial is available from Intel's development site.

IA-64 Tutorials

The following is an overview of the AL460GX MP Server and the BS460GX DP Workstation.

Itanium Systems Overview  Elkhoury, Bassam and Swearingen, Mark  Intel Corporation

An Overview of the Intel IA-64 Compiler
Trimaranastructure for Research in Instruction-Level Parallelism: An Infr