Instruction Sequencing
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Pipeline
EPIC
Instruction Format
Instruction Sequencing
Operating Environments
Predication
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Instruction Group

"a sequence of instructions starting at a given bundle address and slot number and including all instructions at sequentially increasing slot numbers and bundle addresses up to the first stop or taken branch" [3]

Instruction Execution Sequence

  1. Read instruction from memory (fetch)
  2. Read machine state (read)
  3. Perform operation (execute)
  4. Update machine state (update)

Instruction Sequencing Rules

There is no a priori relationship between the fetch of an instruction and the read, execute or update of a dynamically previous instruction
The read of an instruction occurs after the update of every instruction within any preceding instruction group
All instructions have unit latency
A stop imposes at least one unit of latency between instructions preceding and following the stop
Within an instruction group, the read of memory and ALAT state occurs after the update of all preceding instructions in the group
Within an instruction group, the read of register states occurs before the update of all preceding instruction in the group
With few exceptions, RAW (read after write) and WAW (write after write) dependencies are not allowed
With few exceptions, WAR (write after read) exceptions are allowed
The processor may execute any subset (or the entirety) of a legal instruction group concurrently or serially, and may dynamically re-order instructions within an instruction group