Scoreboarding. Here are essential details of 6600 scoreboard: Machine has 10 function units (depending on how you count; text counts 14), each of which is substantially slower than instruction issue (one issue possible per cycle; fastest function unit takes 3 cycles and slowest takes 29). There is a reservation station associated with each functional unit, and one for each register. When an instruction is ``issued'' to a function unit, the unit is reserved, it is set for the instruction it will execute, and the output register is reserved (output registers look a lot like arcs, here). If its data is not available (the register it's looking to for input is reserved) then the instruction is not able to ``go'' until data is available. When data comes available, the function unit reads it from registers (and, in fact, the last piece of data for the instruction is written to both its register and the function unit requiring it at the same time). The function unit does its thing without further supervision by the scoreboard until it's done; at that point it alerts the scoreboard that its data is available. The scoreboard tells it when it can write its data out. Three types of collision: (1) result register or function unit is already reserved. Instruction cannot be issued (note: there are a total of 23 registers out there, including eight 60 bit general purpose registers, seven 18 bit index registers, eight and 18 bit address registers. There are also duplicates of several function units. Hopefully, this type of collision will not be the major factor in limiting the speed of the system). example (all examples assume all registers available at start): X1 <- X2 + X3 X1 <- X4 * X5 (same result register) X1 <- X2 / X3 X4 <- X5 / X6 (same function unit) Note that this scheme has the side-effect of making WAW hazards impossible, since two instructions that write to the same register must occur in sequence. (2) data is not available yet (RAW hazard). In this case the instruction is issued, and following instructions can also be issued (and may even complete!) before the one that has to wait. This is intended to be the main form of conflict determining instruction execution. example: X1 <- X2 / X3 X4 <- X1 * X5 X6 <- X2 + X3 (third instruction will complete before second even starts) (3) (WAR hazard) this one is complex. One operand is available to an instruction that is waiting for a second operand. Unfortunately, another instruction is going to overwrite the available register before the waiting instruction reads it. The instruction causing trouble isn't allowed to finish until after the waiting data is read. example: X1 <- X2 / X3 X4 <- X5 + X1 X5 <- X0 + X6