(10 points) Consider a 33MHz, 32-bit PCI bus. PCI performs all transfers in "burst mode:" that is, once a device has become a bus master and and used one bus cycle to transfer an address, it it is able to make an arbitrary number of data transfers (there is actually a timer function preventing a device from going "rogue" and never releasing the bus) at the rate of one data transfer per bus cycle.
Plot bus throughput (in megabits/second) as a function of transfer size, for 32 bit, 64 bit, 96 bit, and 128 bit transfers.
(20 points) The following 13 bit numbers consist of eight bits of data, four bits of error correcting code, and one parity bit in the order M8 M7 M6 M5 C8 M4 M3 M2 C4 M1 C2 C1 P.
Two of them are correct, two have one-bit errors, and one has a two-bit error. Tell which is which, and correct the two with one-bit errors.
10001111001001011010110010101111011001010101011111010110001101010(20 points) The following bit strings are 32-bit strings, which have had a four-bit cyclic redundancy check computed using the five-bit polynomial from the web page (11001). In both cases, the last four bits of the string are the CRC. One of them is correct, and one is not. Which is which?
01011011010000100010010000010100 100101010001100000110110101001010110 0111(20 points) The text talks about hard drive specifications on pages 646-650. For this problem, we're assuming a controller overhead of 0.
Here's a link to the specifications for the Western Digital WD1200BB disk drive: http://www.wdc.com/en/products/products.asp?DriveID=12
Based on these specifications: