CS473 - HW3 - MIPS and Pipelining

Solutions

MIPS Instruction Coding/Decoding

1. (25 points)

   For each of the following MIPS instructions, assemble the instruction into appropriate MIPS machine code. For the instructions which are actually pseudo-instructions, first translate into an instruction or a sequence of instructions which will accomplish the result, and then assemble the resulting instruction sequence. Your final answer should be in the form of one or more eight-digit hexadecimal numbers.

   1. add $s0, $t8, $a1
      From page A-23, $s0 is $16 (10₁₆), $t8 is $24 (18₁₆), and $a1 is $4.
      From page A-55, the (hexadecimal) fields are 0, 18, 5, 10, 0, 20; combining them gives 03058020
   2. ori $v0, $s1, 0x1234
      From page A-23, $v0 is $2 and $s1 is $17.
      From page A-57, the (hexadecimal) fields are d, 11, 2, 1234; combining them gives 36221234.
   3. beq $s3, $a2, 0x400 the intent here is that the offset be 400₁₆ bytes from the instruction following the beq
      From page A-23, $s3 is $19 and $a2 is $6. We need to divide 0x400 by 4, giving us 0x100 (coincidentally the same in decimal as hex!). From page A-62, the (hexadecimal) fields are 4, 13, 6, 100; combining them gives 12660100.
   4. not $t6, $t7
      This is a pseudoinstruction. We can get the right result by doing an exclusive-or with 0xffffffff; unfortunately, xori won't do it as it doesn't sign-extend the immediate value. So, we'll have to use two instructions; I can think of a couple of clever ways to do it, but the most straightforward is probably with a

      	  addi  $at, $zero, -1
      	  xor   $t6, $at, $t7
      	  

      The first instruction generates the needed 0xffffffff, and the second does the exclusive-or. From page A-23, $t6 is $14 and $t7 is $15. Converting the two instructions gives us fields of

      	  8, 0, 1, ffff
      	  0, 1, f, e, 0, 26
      	  

      Putting them together gives

      	  2001ffff
      	  002f7026
      	  

   5. bge $a3, $s6, 0x800 the intent here is that the offset be 800₁₆ bytes from the instruction following the bge
      Here's another pseudoinstruction. We'll need one instruction to set a proper value in $at, and then we'll branch based on that.
      So, the two-instruction sequence

      	  slt $at, $a3, $s6
      	  beq $at, $zero, 0x800
      	  

      will accomplish it. From page A-23, we have $zero is $0, $at is $1, $a3 is $7, and $s6 is $22. Converting the two instructions gives us the fields

      	  0, 7, 16, 1, 0, 2a
      	  4, 1, 0, 200
      	  

      	  00f6082a
      	  10200200
      	  

   6. abs $t1, $t2
      I can't find a way to do this with less than three instructions: one to copy $t2 to $t1, one to test $t1 to see if it's already positive and skip over the third instruction if it is, and one to subtract the number from 0 to negate it. So we get

      	  addi    $t1, $t2, 0
      	  bgez    $t1, 4
      	  sub     $t1, $zero, $t1
      	  

      From A-23, we have that $t1 is $9, $t2 is $10, and $zero is $0. Converting the instructions gives us

      	  8, a, 9, 0
      	  1, 9, 1, 1
      	  0, 0, 9, 9, 0, 22
      	  

      Combining them, we get

      	  21490000
      	  05210001
      	  00094822
      	  

2. (15 points)

   For each of the following MIPS machine code instructions, disassemble the code back to MIPS assembly code. Use the register use conventions on Page A-23 to translate register numbers (so use register $at, not register $1).

   1. 00221820
      Looking at the first six bits we find the opcode is 0, so this is an R-format instruction and the fields are 0 1 2 3 0 20 (all in hexadecimal). Figure A.19 tells us this is an add instruction, so from page A-55 we find that it's an

      	  add $3, $1, $2
      	  

      Using the conventions from page A-23, the registers translate to

      	  add $v1, $at, $v0
      	  

   2. 304398c3
      Looking at the first six bits we find the opcode is c. From figure A.19, the instruction is an andi (an I-format instruction), so the fields are c 2 3 98c3. From here, we find that the instruction is

      	  andi $3, $2, 0x98c3
      	  

      Following the conventions from A-23, this becomes

      	  andi $v1, $v0, 0x98c3
      	  

   3. 11271234
      This time the opcode is 4, so it's a beq (an I-format instruction. The fields are 4 9 7 1234, so the instruction is

      	  beq $9, $7, 0x48d0
      	  

      Following the conventions from A-23, this becomes

      	  beq $t1, $a3, 0x48d0
      	  

3. (15 points) It turns out that the following instruction cannot be implemented in the MIPS pipeline as presented on Page 470: ori. Why not? Because the instruction requires the immediate operand be 0-extended, and the only data path for it will sign-extend it. Add a multiplexor to the data paths, and a signal to control it from the control unit, which will make it possible.
   Just add a mux that will 0-extend instead of sign-extend the constant.
4. (35 points) Consider the following sequence of MIPS instructions:

   
   lw  $1, 100($4)
   add $5, $6, $7
   or  $8, $9, $1
   sw  $8, 200($12)
   or  $0, $0, $0
   or  $0, $0, $0
   or  $0, $0, $0
   or  $0, $0, $0
   or  $0, $0, $0
   
   

   Using Figure 6.41 as a guide, show the contents of every control and data line in the CPU on every cycle of the execution of this code, starting with an empty pipeline and continuing until the pipeline is full of or instructions. Xeroxing the figure from page 523 and marking it up, or downloading the figure from the text website and marking it up, would be a really good idea. Assume initial register and memory contents as in Problem 6.10.