For each of the following MIPS instructions, assemble the instruction into appropriate MIPS machine code. For the instructions which are actually pseudo-instructions, first translate into an instruction or a sequence of instructions which will accomplish the result, and then assemble the resulting instruction sequence. Your final answer should be in the form of one or more eight-digit hexadecimal numbers.
add $s0, $t8, $a1ori $v0, $s1, 0x1234beq $s3, $a2, 0x400 the intent here is that the
offset be 40016 bytes from the instruction following
the beq
not $t6, $t7bge $a3, $s6, 0x800 the intent here is that the
offset be 80016 bytes from the instruction following
the bge
abs $t1, $t2
For each of the following MIPS machine code instructions, disassemble
the code back to MIPS assembly code. Use the register use conventions
on Page A-23 to translate register numbers (so use register
$at, not register $1).
00221820304398c311271234ori.
Why not? Add a multiplexor to the data paths, and a signal to
control it from the control unit, which will make it possible.
lw $1, 100($4)
add $5, $6, $7
or $8, $9, $1
sw $8, 200($12)
or $0, $0, $0
or $0, $0, $0
or $0, $0, $0
or $0, $0, $0
or $0, $0, $0
Using Figure 6.41 as a guide, show the contents of every
control and data line in the CPU on every cycle of the execution
of this code, starting with an empty pipeline and continuing until
the pipeline is full of or instructions. Xeroxing
the figure from page 523 and marking it up, or downloading the
figure from the text website and marking it up, would be a really
good idea. Assume initial register and memory contents as in
Problem 6.10.