CS 473 - HW7

Solutions

• (50 points) An Intel computer system's PDBR contains 0036a000.

  Here's some of the contents of memory:

  Address	Contents
  00032b90	001d9006
  00061a7c	00248025
  000e3378	003c0067
  0014a80c	5a31f5bc
  001d947c	410fb39e
  0022f80c	772d4d8b
  00248e7c	27c1b87c
  0036a1b0	00032026
  0036a488	000e3027
  0036a4b8	003c3003
  0036a4c4	003fb027
  0036a7cc	00061027
  003c099c	4f13e1d5
  003c330c	0022f003
  003fb82c	0014a006

  And here's the TLB. Assume 32 entries, 4-way set-associative.

  Set	Tag	Valid	Translation
  0	1d63d	1	35b0aa0a
  0	1f7a7	0	17cdde4f
  0	14215	0	6bc6b02e
  0	0442a	1	5f21e80e
  1	11d3b	1	19ec0823
  1	041dc	1	78f6544b
  1	11a34	0	1cfa9a1d
  1	0de6d	1	4264122c
  2	0ab64	1	0a309825
  2	195bc	1	7276004a
  2	091fa	0	56943633
  2	13c04	1	1c81fc3c
  3	09718	1	0022f003
  3	1cc01	1	6d238438
  3	1b510	1	18229c7d
  3	1bdb3	1	629cac10
  4	011ff	0	315fda58
  4	0ac9c	1	3d454273
  4	0bec8	1	0a1c9c07
  4	156ed	1	558e8254
  5	158b8	1	1b5c3e5e
  5	18f6b	1	7e45f20f
  5	18ca7	1	0f66e856
  5	16f20	0	02222448
  6	0f358	0	444c7a75
  6	19155	0	2ba1147e
  6	0911b	1	003c0067
  6	0183d	1	6cb95a68
  7	15bb0	0	0dfc9877
  7	1f837	1	55b36c43
  7	07b0b	1	1a76d008
  7	0f9d3	0	11f77252

  Given all that, what happens when a user tries to write to each of the following addresses (you may get page faults, you may get protection faults, you may get TLB hits or misses...)

  • 1b2e447c

    First, we try the TLB. Divide the address into tag, index, and byte offset as 0365c 4 47c. No tag matches, so TLB miss.

    So divide it up for the tables: 1b0 b90 47c (I'm using the offsets - that's index * 4 - into the directory and page table here). The directory entry is at 0036a1b0. The directory entry contains 00032026. The least significant bit is a 0, so the page table is not present. We have a page fault.

  • 4c60b80c

    First, we try the TLB. Divide the address into tag, index, and byte offset as 098c1 3 80c. No match again, so TLB miss.

    So divide it up for the tables: 4c4 82c 80c. The directory entry is at 0036a4c4. The directory entry contains 003fb027. This time the page table is present, and the U and W bits are also 1; we can go on to the next step.

    The page table entry is at 003fb82c. The page table entry is 0014a006. The P bit is 0, so we have another page fault.

  • 4b8c380c

    TLB: 09718 3 80c. This time we get a tag match on a valid entry; the entry contains 002f003. No page fault this time due to the present bit being 1; unfortunately, the U bit is 0, so the page is not user-accessible; protection fault.

  • 7ce9fe7c

    TLB: 0f9d3 7 e7c. We've got a tag match, but the entry isn't valid. Darn, TLB miss.

    Tables: 7cc a7c 80c. The directory entry is at 0036a7cc; the directory entry is 00061027; no faults yet, so the page table entry is at 00061a7c; it contains 00248025. This time the W bit is 0; we have another protection fault.

  • 488de99c

    TLB: 0911b 6 99c. TLB hit; the entry contains 003c0067. It is present, and users can write to the page. Success! We write our new value to physical address 003c099c.

• (10 points) What is the maximum throughput of a 33 MHz, 32-bit PCI bus performing 32 bit transfers? What is it for 128 bit burst-mode transfers?

  The theoretical maximum throughput of PCI is 33*4 = 132 MB/sec (that's 33 MHz times 32 bits divided by 8 bits/byte). PCI is multiplexed; making 32 bit transfers we have to alternate address-data-address-data etc. So we can only use 50% of the cycles, so we only get 66 MB/sec (that's the same as 528 Mb/sec, if you carried out the calculation in bits).

  For 128 bit transfers, we need an address cycle for every four data cycles. So we get 80% of the theoretical maximum, or 105.6 MB/sec (844.8 Mb/sec).

• (10 points) What's the average rotational latency of a 7200 RPM disk drive? If the disk's average total access time, not including controller overhead, is 8.5 msec, what is its head seek time?

  It's a 7200RPM drive; 7200/60 is 120 RPS. One rotation takes 1/120 sec = 8.33 msec. The average rotational latency will be half this, so it's 4.17 msec.

  If the total access time is 8.5 msec, the head seek time is 8.5 - 4.17 = 4.83 msec.

• (30 points) Define an Intel 810 triangle vertex with the following properties:
  • Location: (16.0, 16.0, 0.5)
  • Enable wireframe for all edges of triangle
  • Z bias: 0
  • W: 1
  • (A, R, G, B) = (1.0, 255, 0, 0)
  • Fog factor: 128
  • Specular blue: 0
  • Texture coordinates: (0, 0, 0, 0)

  Doubleword	Contents
  0	16.0, 1, 1, 1
  1	16.0
  2	0.5
  3	0
  4	1
  5	255, 255, 0, 0
  6	128, 0
  7	0
  8	0
  9	0
  10	0

  (I really should have required the bits on this one...)