CS 473 HW4 Solutions

Suppose the following sequence of MIPS instructions is to be executed:

beq   $0, $5, 100
lw    $1, 200($0)
addi  $3, $4, 100
sub   $5, $2, $3
sw    $5, 300($4)

1. (25 points) Assume that initially the pipeline is empty, and that the assumptions in problem 6.10 from the book hold. Based on those assumptions, give the contents of every pipeline register (both control and data, both relevant and irrelevant) at the end of the fifth cycle of execution. Use Figure 6.65 as your model for the pipeline.
2. (5 points) Why will this instruction not be able to execute the last instruction (the sw) successfully?

   Of course, it turned out it could. It wouldn't have been able to handle a lw followed by an immediate sw, with the register being loaded in the lw being read immediately in the sw, because that would require a forwarding path from the MEM/WB pipeline register to the data input to the data memory.

3. (25 points) Modify the pipeline in Figure 6.65 as follows:
   1. Move the forwarding unit from the EX stage to the ID stage. How will this affect the size of each of the pipeline registers? Does it end up making the total size of the pipeline registers larger or smaller?

      Sorry, after getting the Problem 1 figure scanned and down to a reasonable size, I don't have time to draw a figure for this one. The basic steps will be:

      1. Move the forwarding unit as stated.
      2. The connections all come from one cycle upstream of where they did previously: the register number inputs on the left side of the forwarding unit come directly from the instruction fields; the inputs that currently come from the EX/MEM pipeline registers come from the ID/EX pipeline register or the RegDst mux, as appropriate; the inputs that currently come from the MEM/WB pipeline register come from the EX/MEM pipeline register.
      3. The outputs that were going directly to the output muxes go intput ID/EX pipeline register instead.

      It would make the pipeline registers smaller: ten bits of register number would no longer have to be in the ID/EX pipeline register, 4 bits of mux control would have to be added to that register. There is no difference in the sizes of the EX/MEM and MEM/WB registers, since the values we tap from them are needed for other purposes.

      Oh, one last thing - I haven't a clue why the text is putting instruction bits 20-16 in the ID/EX pipeline register twice. If we assume rational behavior, this change only makes a one bit difference in the size of the ID/EX register, rather than six.

   2. Add a forwarding mux to the write data input of the data memory. Give the equations for controlling this mux.

      The mux goes on the Write data input to the data memory. Its inputs are the Write data field of the EX/MEM pipeline register, and the Read data field of the MEM/WB pipeline register. The control equation is

      if ((MEM/WB.RegisterRd != 0) &&
          (MEM/WB.MemToReg == 1) &&
          (MEM/WB.RegWrite == 1) &&
          (MEM/WB.RegisterRd == EX/MEM.RegisterRd))
          ForwardMem = 1;
      			

      Notice that this also requires the RegDst field to be defined as 0 on a sw instruction. Oh, one other thing - I'm answering this as independent from the answer to the previous question. Of course, it could also have answered assuming the forwarding unit was in the ID stage.

   Note: neatness counts on this problem. If it's hard for the TA to read, it's hard for her to grade.