CS 473 - HW4

More Pipelining

Due Wednesday, February 27, 2002

Suppose the following sequence of MIPS instructions is to be executed:

beq   $0, $5, 100
lw    $1, 200($0)
addi  $3, $4, 100
sub   $5, $2, $3
sw    $5, 300($4)

1. (25 points) Assume that initially the pipeline is empty, and that the assumptions in problem 6.10 from the book hold. Based on those assumptions, give the contents of every pipeline register (both control and data, both relevant and irrelevant) at the end of the fifth cycle of execution. Use Figure 6.65 as your model for the pipeline.
2. (5 points) Why will this instruction not be able to execute the last instruction (the sw) successfully?
3. (25 points) Modify the pipeline in Figure 6.65 as follows:
   1. Move the forwarding unit from the EX stage to the ID stage. How will this affect the size of each of the pipeline registers? Does it end up making the total size of the pipeline registers larger or smaller?
   2. Add a forwarding mux to the write data input of the data memory. Give the equations for controlling this mux.
   Note: neatness counts on this problem. If it's hard for the TA to read, it's hard for her to grade.