The following table gives some of the memory contents of a computer using Intel's virtual memory scheme:
The PDBR contains 00061000
| Address | Data |
|---|---|
000610bc | 002cb023 |
00061138 | 002be045 |
000613d0 | 00326007 |
00061468 | 0017c025 |
000615c0 | 0031b025 |
00077a60 | 76741af0 |
00091c60 | 7cb4c217 |
0017c200 | 00091023 |
001ea670 | 2b3bd4e5 |
002be1e8 | 002da045 |
002cbf58 | 00077003 |
002d77c0 | 3cbbfd39 |
002da2fc | 4878eaed |
0031b028 | 001ea042 |
00326004 | 002d7007 |
Assume this computer has a 32-entry, 4-way set-associative TLB. Here are the complete contents of the TLB:
| Set | Tag | Valid | Entry |
|---|---|---|---|
0 | 19392 | 0 | 3f25083a |
| 01a04 | 1 | 54477650 |
| 00e40 | 1 | 5eb4f00e |
| 045d1 | 0 | 00663c18 |
1 | 033c8 | 0 | 4801fc12 |
| 10fed | 0 | 699e1e7b |
| 07a00 | 1 | 002d7007 |
| 0d349 | 0 | 70f2fc54 |
2 | 0270f | 0 | 35fe2e26 |
| 13286 | 0 | 01a8dc45 |
| 15145 | 0 | 1edfda61 |
| 05a00 | 1 | 1bcdfe67 |
3 | 1d1d0 | 1 | 68fafa68 |
| 0c35e | 0 | 69906e06 |
| 100f6 | 0 | 29b4fc04 |
| 0fd08 | 0 | 53ac1a35 |
4 | 11c83 | 1 | 294a6e4c |
| 05184 | 0 | 3a8ee035 |
| 14dd8 | 1 | 3df5881a |
| 17bff | 0 | 3a770c5a |
5 | 058c4 | 1 | 0ab8222d |
| 03426 | 1 | 0a9b5204 |
| 0340d | 1 | 4458901b |
| 12e75 | 0 | 698e1604 |
6 | 19d7c | 0 | 2fa3ce34 |
| 017fa | 0 | 65f89652 |
| 0b5b5 | 0 | 283e847b |
| 12502 | 1 | 34f1466e |
7 | 005b7 | 1 | 58b9840d |
| 18f51 | 0 | 5584f233 |
| 09bac | 1 | 5d33b41f |
| 0be59 | 1 | 2eeace0a |
For each of the following addresses, assume an attempt is made to read four bytes from the given address, in User mode. What happens? In the event of a protection failure or page fault, be sure to tell at what level the failure occurs. If data is successfully returned, tell what the value is. Tell whether there is a TLB hit or miss.