CS473 - HW6

Cache

Due Wednesday, October 30, 2002

1. (15 points) Consider a computer with a 32 bit address. For each of the following cache organizations, describe the division of the address into tag, index, and byte offset fields:

   1. 8KB, direct-mapped, 4 byte line
   2. 256KB, 4-way set-associative, 16 byte line
   3. 2KB, fully-associative, 64 byte line

2. (40 points)

   Assume you have the following string of memory addresses (these are byte addresses in a machine with an absurdly small eight bit memory address space): 0x64, 0x68, 0x6c, 0x70, 0x68, 0xfc, 0x00, 0x68, 0x54, 0x58, 0x5c, 0x60, 0x64, 0x68, 0x6c, 0x70, 0x74, 0x78, 0x7c, 0xf8

   For each of the following cache organizations,

   1. Give the breakdown of an address into tag, index, and byte offset
   2. For each memory access, tell which cache block the address maps to and whether the result is a hit or a miss. If it's a miss, classify it as a compulsory miss, a capacity miss, or a conflict miss.

   The cache organizations are:

   Organization	Total Size	Block Size	Associativity
   a.	64	4	1
   b.	64	16	1
   c.	64	4	4
   d.	64	16	4

   Notes:

   • All sizes are in bytes
   • Yes, the part d is fully-associative
   • For all of the set-associative organizations, use an LRU replacement algorithm.
   • For each organization, assume the cache is empty initially (and that you fill it as you process the reference string).