Give the machine code for each of the following instructions. In some cases, they are actual hardware instructions; in others, they are pseudoinstructions, and will need to be translated into one or two real instructions (one of them actually takes three).
0 (like 017) in which case they
are octal, unless they start with 0x (like
0x1a) in which case they are hexadecimal.
add $1, $2, $3
is translated as
00430820
(you don't need to bother with the 0x)
You are likely to find Appendix A very useful. The
translation between register numbers like $a2 and their
``real'' numbers ($6 in this case) is in Append A.6.
addi $1, $9, 100lui $s1, 010slt $5, $a1, $t1sw $9, 200($s3)beq $12, $17, 0x100 (assume 0x100 is
the actual offset to the target instruction.
sge $5, $6, $7li $5, 0x1234abcd
abs $3, $a3
Assume the instructions in the first problem are a program,
starting at address 0x400. At the end of the first
cycle of execution, the PC will contain 0x404, the
first instruction has been read into the IF/ID pipeline
register, and the contents of the rest of the data paths are
unknown. Show the contents of the data paths following cycles
2, 3, 4, and 5. I don't think I created any hazards with the
sequence of instructions I gave you; if I did, just ignore
them. Give the contents of every field of
every pipeline register in the data paths (that's
important: just data, not control) that you can determine, whether
it's useful to the instruction or not. Follow the assumptions
for problem 6.10 in the book for initial register comments,
except the PC (which I gave you above).
You'll probably want to make several photocopies of the top half of page 452. Please scale them up to fill a whole page!
In the MIPS as described so far, it is impossible to implement an
addiu instruction. Why? Add a mux to make it
possible.