CS 473 - HW3

MIPS

Due Monday, September 23, 2002

  1. (80 points)

    Give the machine code for each of the following instructions. In some cases, they are actual hardware instructions; in others, they are pseudoinstructions, and will need to be translated into one or two real instructions (one of them actually takes three).

    You are likely to find Appendix A very useful. The translation between register numbers like $a2 and their ``real'' numbers ($6 in this case) is in Append A.6.

    1. addi $1, $9, 100
    2. lui $s1, 010
    3. slt $5, $a1, $t1
    4. sw $9, 200($s3)
    5. beq $12, $17, 0x100 (assume 0x100 is the actual offset to the target instruction.
    6. sge $5, $6, $7
    7. li $5, 0x1234abcd
    8. abs $3, $a3
  2. (80 points)

    Assume the instructions in the first problem are a program, starting at address 0x400. At the end of the first cycle of execution, the PC will contain 0x404, the first instruction has been read into the IF/ID pipeline register, and the contents of the rest of the data paths are unknown. Show the contents of the data paths following cycles 2, 3, 4, and 5. I don't think I created any hazards with the sequence of instructions I gave you; if I did, just ignore them. Give the contents of every field of every pipeline register in the data paths (that's important: just data, not control) that you can determine, whether it's useful to the instruction or not. Follow the assumptions for problem 6.10 in the book for initial register comments, except the PC (which I gave you above).

    You'll probably want to make several photocopies of the top half of page 452. Please scale them up to fill a whole page!

  3. (20 points)

    In the MIPS as described so far, it is impossible to implement an addiu instruction. Why? Add a mux to make it possible.


Last modified: Wed Sep 18 21:18:31 MDT 2002