1. (A) The parts that are not relevant is:
* 32 bit virtual address
* 4 way set associative
* 4 MB cache size
All the rest parts are relevant.
1. (B) Key to the problem is trying to minimize the average memory access time (AMAT).
AMAT = Cache Access Time (CAT) + ( 1 - hit rate ) * miss penalty
Cache A AMAT = 1 + 0.01 * 10 = 1.1
Cache B AMAT = 1 + 0.005 * 17 = 1.085
Since 1.085 < 1.1, then Cache B should be used.
2.
On Cycle 1, "mul a, b, 2" "sub b, b, d"
On Cycle 2, "mul c, a, 4" "LT p1, p2, a, b"
On Cycle 3, "p1: add d, c, 5", "p2: sub d, b, 4"
3 A.
Hidden Assumption:
** In processor 1, i reads before j
** In processor 2, j reads before i
If processor 2 and 3 runs before 1 and 4, then neither k or l being assigned.
If processor 4 runs before 2 and 3, l gets assigned.
If processor 2 runs first, and then followed by 4 qnd 3, l gets assigned.
If processor 3 runs first, and then followed by 1 and 2, k gets assigned.
So, it is possible that either for k to be assigned 3 or for l to be
assigned 4. But in orfer to let them both assigned. Following conditions
need to be held:
1) processor 2 has to be run before processor 3.
2) processor 3 has to be run before processor 2.
We realize that it is not possible to have all these two conditions
coexisting, so it is impossible to let k and l are both assigned.
3.B.
For weak ordering consistency model,
processor 4 has to see processor 2 running first; meanwhile,
processor 1 has to see processor 3 running first;
So, it is possible for both k to be assigned 3, and 1 to be assigned 4,
on a single run.
3.C.
Because we want to make sure that k will be assigned 3, the processors running order should be 3, 1, 2.
P1 P2 P3 P4
j = 2;
Barrier Barrier Barrier Barrier
if (i < j)
k = 3;
Barrier Barrier Barrier Barrier
i = 2; if ( j < i)
l = 4;