Department of Computer Science Qualifying Examination
Computer Architecture
Fall, 1999

The intent is that it should take approximately one hour to answer the questions on this exam. The questions are equally weighted.

1. Four of the classic network topologies are the bus, ring, crossbar, and hypercube.

A.Compare the bandwidth, latency, and cost of these topologies.

B.How have developments in network implementation, in particular hardware cost and wormhole routing, affected the importance of the metrics in part A?

2. Suppose you have a computer system with the following characteristics:

Address Width 43 bits
Page Size 8K bytes
Size of Page Table Entries 8 bytes
Number of Entries in Page Table 1K
Size of Level 1 Cache 16K bytes
Level 1 Cache Block Size 16 bytes
Level 1 Cache Associativity 8-way


A. How many levels of page tables are there (all levels of paging have the characteristics shown above)

B. How is an address divided into fields for virtual memory lookups (be sure to give the width of each field)?

C. How is an address divided into fields for level 1 cache lookups (be sure to give the width of each field)?

D. If the cache is in the physical address space, is it feasible to do a TLB lookup for the virtual memory at the same time as a cache lookup?

3. Acquiring and releasing locks on shared data can be thought of as claiming and relinquishing ``ownership'' of the data. When you request a lock you request ownership; when you release the lock you are relinqushing the ownership. How does this relate to message passing? What operation corresponds the acquiring a lock? What operation corresponds to releasing a lock? Which mechanism gives the programmer more control over the ownership of the data?

4. The following somewhat provocative statement appeared in the comp.arch newsgroup:

Subject: Re: Is RISC dead? (was: Re: K7's FP performance inches past P-III's)

Date: 1999/05/19

Author: Piercarlo Grandi

Well, my take here (and I said so in "comp.arch" quite a while ago) is that _architecture_ is dead: with essentially infinite silicon/design budgets virtually any architecture, including x86, can be made to perform; in other words only implementation matters.

Have we reached the point that the instruction set is irrelevant, because with current technology any pig can be made to fly? Are some aspects of the architecture still important, and others less so? Justify your answer.
 
 


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